SAN JOSE, Calif.–(BUSINESS WIRE)–Oct 7, 2020–
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the immediate availability of a complete, silicon-proven Cadence ® IP supporting the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process. The multi-standard IP includes Cadence PHY and controller Design IP and Verification IP (VIP) and supports a wide variety of applications including data center, storage, artificial intelligence/machine learning (AI/ML) and hyperscale computing. Customers using Cadence and TSMC technologies can design advanced-process chips that connect to multiple memory types more quickly and with low risk.
For more information on the Cadence IP for DDR, please visit www.cadence.com/go/ddrippr.
Cadence’s IP collaboration with TSMC is critical in today’s market landscape. For example, the union of DDR5 and LPDDR5 protocol solutions in the same memory interface IP offers a high-speed, scalable solution from large to small memory footprints. The goal of this Cadence IP is to make